Programmable logic devices (e.g., field programmable gate arrays (FPGAs)) are used in a wide variety of applications. A typical programmable logic device (PLD) includes a plurality of logic blocks that can be programmed to perform desired functions. The PLD may also include embedded blocks of volatile memory (e.g., block SRAM) to provide, for example, temporary storage during operation or to store a large amount of data during configuration that may be used by the logic during normal operation.
One drawback of a conventional PLD is that the embedded blocks of volatile memory may not be sufficient in some respect for a desired application and may lead to routing congestion. Consequently, some conventional PLDs also allow the SRAM forming the individual lookup tables (LUTs) within the logic blocks of the PLD to be used as memory, a technique commonly referred to as distributed memory (i.e., using the LUT memory within the homogenous logic blocks that are distributed throughout the PLD rather than using a few large volatile memory blocks as with the embedded blocks of volatile memory).
However, the conventional distributed memory approach often results in unused circuitry and resources for the typical application and limited flexibility in terms of selecting the desired amount of available distributed memory for a given application. Furthermore, the process of programming the distributed memory using an external bitstream is often undesired for certain applications. As a result, there is a need for improved memory techniques for programmable logic devices.